The present invention relates to an improved data transfer system that utilizes a hardware interconnection between two direct memory access channels to provide high speed transfer of data between two portions of a computer memory system, without intermediate mass storage.
In a range of complex data processing tasks, scratch tapes or other mass storage devices are used to store intermediate processing results. For example, many seismic data processing tasks consist of a series of steps that are applied to a set of seismic data that are initially stored on magnetic tape. Each step is a separate program which may, for example, read a set of input data from magnetic tape (generated by the preceding step) process the input data, and then generate a set of output data on magnetic tape (which is subsequently supplied as an input to the next step). Such intermediate scratch tapes are often used because the volume of data is large and they allow each step to be developed as a separate entity. Seismic data processing tasks may consist of ten or more individual steps, each linked to the next by a corresponding scratch tape.
Such extensive use of scratch tapes represents a significant limitation on execution speed, since the reading and writing of such tapes is both time-consuming and susceptible to errors.
In the past, a number of approaches have been proposed for simplifying the sequential processing of digital information. For example, the UNIX system described by B. W. Kernighan and J. R. Mashey in the article entitled, "The UNIX Programming Environment"; IEEE (Computer), April 1981, pp. 12-24, utilizes an operating system which facilitates the linking of sequential processing steps. However, no hardware is described in this paper to provide high speed data transfer between two portions of computer memory.
Pirz U.S. Pat. No. 4,149,242 discloses an interface apparatus for multiple sequential processors in which a plurality of processors, each with its own memory, are linked in series by a chain of transfer units. The operation of the processors is synchronized carefully such that data transfers between adjacent processors occur simultaneously. Thus, each of the processors executes its task with the data stored in its respective memory, and then the data are moved from one memory to the next simultaneously. Thus, each processor must complete its respective task within the time period between adjacent data transfers so that the next data transfer can take place. In this sense all of the processors are required to run in synchrony.
Neither of these two prior art approaches utilizes specifically designed hardware to allow two asynchronously running programs to be linked together for high speed data transfer therebetween, without scratch tapes or other intermediate mass storage.